An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM allows a memory circuit to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
Another form of memory is the content addressable memory (CAM) device. A CAM is a memory device that accelerates any application requiring fast searches of a database, list, or pattern, such as in database machines, image or voice recognition, or computer and communication networks. CAMs provide benefits over other memory search algorithms by simultaneously comparing the desired information (i.e., data in the comparand register) against the entire list of pre-stored entries. As a result of their unique searching algorithm, CAM devices are frequently employed in network equipment, particularly routers and switches, computer systems and other devices that require rapid content searching.
In order to perform a memory search in the above-identified manner, CAMs are organized differently than other memory devices (e.g., DRAM and SRAM). For example, data is stored in a RAM in a particular location, called an address. During a memory access, the user supplies an address and reads into or gets back the data at the specified address.
In a CAM, however, data is stored in locations in a somewhat random fashion. The locations can be selected by an address bus, or the data can be written into the first empty memory location. Every location has a pair of status bits that keep track of whether the location is storing valid information in it or is empty and available for writing.
Once information is stored in a memory location, it is found by comparing every bit in memory with data in the comparand register. When the content stored in the CAM memory location does not match the data in the comparand register, the local match detection circuit returns a no match indication. When the content stored in the CAM memory location matches the data in the comparand register, the local match detection circuit returns a match indication, e.g., a match flag. If one or more local match detection circuits return a match indication, the CAM device returns a “match” indication. Otherwise, the CAM device returns a “no-match” indication. In addition, the CAM may return the identification of the address location in which the desired data is stored or one of such addresses if more than one address contained matching data. Thus, with a CAM, the user supplies the data and gets back the address if there is a match found in memory.
Many current applications utilize ternary CAMs, which are capable of storing three logic states. For example, the three logic states are logic “0”, logic “1”, and “don't care”. Therefore, such CAM cells require two memory cells to store the logic states, as well as a comparison circuit for comparing stored data with search data provided to the CAM.
FIG. 1 depicts a six transistor (6T) dynamic ternary (DRAM) CAM cell 100 of the prior art. The cell 100 has an “x” bit and a “y” bit. For the x bit, data is written to and read out of the cell 100 via bitline BLx 110, access transistor 160 and storage capacitor Cx 140. For the y bit, data is written to and read out of the cell 100 via bitline BLy 112, access transistor 162 and storage capacitor Cy 142. The access transistors 160, 162 are controlled by a common wordline 132. It should be understood that the storage capacitors can be discrete components or the parasitic capacitance of the line 132. Alternately, other storage or memory devices may be used to store data in the cell 100. Although not shown, other memory cells 100 in a column of a memory array are coupled either to bitline BLx 110 and bitline BLy 112 or bitline BLx* 114 and bitline BLy* 116. Although CAM cell 100 is shown as a DRAM CAM cell, the CAM cell may also be implemented using other types of memory storage, e.g., the CAM cell may use SRAM memory cells.
To store a logic “0” in the cell 100, a “1” must be written into the x bit, and a “0” must be written into the y bit of the cell 100. To store a logic “1” in the cell 100, a “0” must be written into the x bit and a “1” must be written into the y bit of the cell 100. If a “0” is stored in both the x and the y bits of the cell 100, then the cell 100 will be masked for a search operation. If a “1” is stored in both the x and the y bits of the cell 100, then the cell 100 will always indicate a mismatch for search operations.
During a search operation, a search key/word is applied to search datalines SDx 120, SDy 122, each of which is coupled to the gate terminal of compare transistors 174, 176, respectively. A first source/drain of the compare transistors 174, 176 is coupled to a common matchline 130. A second source/drain of the transistors 174, 176 is coupled to a first source/drain of transistors 170, 172, respectively. Each transistor pair 174-170 and 176-172 is referred to as a compare “stack.” The applied search key is compared to data stored in the cell 100 to see if there is a match. To search for a “0,” SDx is set to 0 and SDy is set to 1; to search for a “1,” SDx is set to 1, and SDy is set to 0.
FIG. 2 shows a CAM array 200 and associated circuits 250, 252, 254, 256. The array 200 includes a plurality of CAM cells 100 organized as a plurality of rows and columns. Each row of CAM cells 100 is coupled to a respective wordline 132 and matchline 130, where every CAM cell 100 in the same row is mutually coupled to the wordline 132 and matchline 130 corresponding to the row. Each column of CAM cells 100 is coupled to a respective search dataline SDx 120, SDy 122, and to bitlines BLx 110, BLy 112, BLx* 114, BLy* 116, where every CAM cell 100 in the same column is mutually coupled to the search dataline SDx 120, SDy 122 and to either bitline BLx 110 and bitline BLy 112 or bitline BLx* 114 and bitline BLy* 116 corresponding to the column.
Every wordline 132 is coupled to access/decode circuit 254 and to a respective wordline driver 284. Every matchline 130 is coupled to access/decode circuit 256 and to a respective sense amplifier 286. Every search dataline SDx 120, SDy 122 is coupled to access/decode circuit 252 and to a respective search data driver 282. Every bitline BLx 110, BLy 112, BLx* 114, BLy* 116 is coupled to access/decode circuit 250.
It is known to orient the matchlines 130 substantially parallel to the wordlines 132 in the conventional CAM architecture (e.g., FIGS. 1 and 2). However, signals and other currents carried on the matchline 130 can create noise on an adjacent wordline 132. Noise on a wordline 132 can affect a charge stored on an adjacent capacitor Cx 140 or Cy 142 (FIG. 1), as the noise may cause the charge on the capacitor to leak. Accordingly, there is a desire and need to reduce noise on a CAM wordline that may be caused by the matchline.
It is also known to orient the search datalines SDx 120, SDy 122 substantially parallel to bitlines BLx 110, BLy 112, BLx* 114, BLy* 116 in the conventional CAM architecture (e.g., FIGS. 1 and 2). However, signals and other currents carried on a search dataline SDx 120, SDy 122 can create noise on an adjacent bitline BLx 110, BLy 112, BLx* 114, BLy* 116. In the operation of a CAM array, since a bitline is used to sense data and the complement of the bitline is used as a reference, if one of these two bitlines receives noise and the other does not, then data on the bitlines will be read or written incorrectly. Accordingly, there is a desire and need to reduce noise on a CAM bitlines that may be caused by the searchline.
Storage of a signal in a DRAM memory cell is inherently more unstable than storing a similar charge in a SRAM memory cell. A DRAM cell is more sensitive to noise, while the SRAM has a strong resistance to noise. Consequently, spurious noise in a memory array is more likely to perturb a DRAM memory cell than a SRAM memory cell. Therefore, it is desirable to reduce the effect of spurious noise in the circuitry of the DRAM CAM array.